The increased operating speed of central processing units (CPUs) and other peripheral large scale integrated (LSI) circuits has led to the wider use of synchronous semiconductor memory devices. Synchronous semiconductor memories are usually high-speed memories that can execute "burst" operations in synchronism with an external clock signal. Burst operations can allow access to multiple memory locations with the application of a single address. Synchronous memories can include dynamic random access memories (DRAMs) and static RAMs (SRAMs), to name just two examples.
Conventional synchronous semiconductor memories may receive various input signals. Input signals may include a clock signal CLK and a clock enable signal CKE. In addition, other input signals may include address signals groups (A0 to An), input/output data groups (DQ0 to DQm), a row address strobe signal RAS, a column address strobe signal CAS, and a write enable signal WE.
Synchronous semiconductor memories can generate an internal clock signal having a constant pulse width that corresponds to the external clock signal CLK and the clock enable signal CKE. A synchronous semiconductor memory can operate in synchronism with such an internal clock signal. Control commands may be entered by the application of various external input signals in synchronism with the external clock signal. As just one example, control commands may be entered that result in a burst mode of operation.
In addition to executing various operations in response to various control commands, synchronous memories may also be capable of switching to a "power-down" mode according to the application of an external signal, such as a CKE signal. A power-down mode may reduce the power consumption of a synchronous memory.
Referring now to FIG. 8, a block diagram is set forth showing a clock control section of a conventional synchronous semiconductor memory. The clock control section is disclosed in, as one example, Japanese Patent Application Laid-Open (Kokai) No. Hei 6-290583. In FIG. 8, the clock control section of the conventional synchronous semiconductor memory is designated by the general reference character 800, and includes first and second initial circuits (802 and 804), and first, second, and third control circuits (806, 812 and 818, respectively). The conventional clock control section 800 receives an external clock signal CLK as well as a clock enable signal CKE. In response to the various input signals, the conventional clock control section generates an internal clock signal .phi.5 and a control signal .phi.7. The .phi.5 and .phi.7 signals may be supplied to other internal circuits of the synchronous semiconductor memory.
As shown in FIG. 8 the clock control circuit is designated by the general reference character 800, and is shown to include a first initial circuit 802 that may receive the external clock signal CLK, and compare it with a reference voltage VREF. The comparison result is then amplified and output as a signal .phi.1. A second initial circuit 804 may receive the clock enable signal CKE, and compare it with a reference voltage VREF. The comparison result is then amplified and output as a signal .phi.2. The first and second initial circuits (802 and 804) may include transistors arranged in a current mirror configuration with a pair of compare transistors.
A first control circuit is set forth in FIG. 8 by the reference character 806, and is shown to include a first one-shot signal generating circuit 808 and a second one-shot signal generating circuit 810. The first one-shot signal generating circuit 808 generates a period signal .phi.3. Period signal .phi.3 can have a constant pulse width, and may vary periodically in synchronism with the external clock signal CLK. The second one-shot signal generating circuit 810 receives signal .phi.1 and another signal .phi.4, and generates an internal clock signal .phi.5. Internal clock signal .phi.5 can have a constant pulse width, and may be mask-controlled in synchronism with the external clock signal CLK and the clock enable signal CKE. The internal clock signal .phi.5 may be considered mask-controlled in that the internal clock signal .phi.5 may be synchronous with the CLK signal in response to a CKE signal of a first logic value, but may be maintained at a constant logic value in response to a CKE signal of a second logic value.
The period signal .phi.3 and internal clock signal .phi.5 may be designed to have low pulse widths of the same length. Further, the signals .phi.3 and .phi.5 can be utilized to control the synchronous operation of other circuits. For example, period signal .phi.3 can be designed to drive a second control circuit 812, while internal clock signal .phi.5 can be designed to drive all other internal circuits (not shown).
In a power-down mode, the CKE signal can transition to a low value. One cycle following such a CKE signal transition, internal clock signal .phi.5 can be placed in an inactive (high, for example) logic level. As a result, the synchronous operation of the internal circuits can stop, thereby reducing current consumption.
The second control circuit 812 of the conventional clock control section 800 is shown to include a D-type flip-flop 814 and a D-type latch circuit 816. The D-type flip-flop 814 can receive the signal .phi.2 as one input, and provide a signal .phi.6 as an output, in synchronism with the period signal .phi.3. The .phi.6 signal can be delayed with respect to the .phi.3 signal.
The D-type latch circuit 816 can receive the .phi.6 signal and output the signal .phi.4 with a further delay of a half-cycle, in synchronism with the period signal .phi.3.
The conventional clock circuit 800 also includes a third control circuit 818. The third control circuit 818 can include a logic circuit that receives the .phi.2, .phi.4 and .phi.6 signals and provides a control signal .phi.7. The control signal .phi.7 can become active (low, for example) immediately following a low-to-high transition in the clock enable signal CKE. The control signal .phi.7 may then become inactive (high, for example) one cycle following a high-to-low transition in the clock enable signal CKE. The control signal .phi.7 may be utilized by other initial circuits (not shown). Such other initial circuits can compare other external input signals with a reference signal voltage VREF, and then amplify the comparison result.
A brief description will now be given of the operation of a conventional clock control section of a semiconductor memory set forth in FIG. 8.
The conventional synchronous memory can receive the system clock of the device (such as the external clock signal CLK), as well as the clock enable signal CKE, for controlling the power-down mode. The CLK and CKE signals are compared within the first and second initial circuits (802 and 804, respectively) to a reference signal voltage VREF. The comparison results are amplified and output as the signals .phi.1 and .phi.2, respectively.
The signals .phi.1 and .phi.2 are received by the first and second control circuits (806 and 812, respectively). Within the first control circuit 806, the first one-shot generating circuit 808 receives the .phi.1 signal, and in response thereto, outputs the period signal .phi.3. In the example of FIG. 8, the period signal .phi.3 can have a constant pulse width and vary in synchronism with the signal .phi.1. The period signal .phi.3 is output to the second control circuit 812.
The D-type flip-flop and D-type latch (814 and 816) delay the signal .phi.2 in synchronism with the period signal .phi.3 to generate output signal .phi.6. The signal .phi.2 can be delayed further to generate the .phi.4 signal, which can be delayed by a half clock cycle with respect to the .phi.6 signal.
The third control circuit 818 generates the control signal .phi.7 in response to the .phi.2, .phi.6, and .phi.4 signals. The control signal .phi.7 will become active (low, for example) essentially immediately after the clock enable signal CKE transitions high. The control signal .phi.7 will become inactive (high, for example), essentially one clock cycle after the clock enable signal CKE transitions low.
When the control signal .phi.7 becomes low essentially immediately after the clock enable signal CKE transitions high, other initial circuits (not shown) can be activated. The other initial circuits can compare external input signals with a reference signal voltage VREF, and then amplify and output the comparison results. In addition, following a low-to-high transition in the clock enable signal CKE, the .phi.4 signal can transition low. Such a transition in the .phi.4 signal may occur as much as about one clock cycle following a transition in the CKE signal.
Within the second one-shot signal generating circuit 810, the resulting .phi.1 and .phi.4 signals allow internal clock signal .phi.5 to be generated. Internal clock signal .phi.5 can be activated about one clock cycle following a low-to-high transition in the clock enable signal CKE. The internal clock signal .phi.5 may be supplied to internal circuits (not shown) to allow such circuits to operate in synchronism with the external clock signal CLK.
In this way, a synchronous semiconductor memory can input external input signals, such as address signal groups A0 to An, input/output data groups DQ0 to DQm, a RAS signal, a CAS signal and a WE signal, to name a few examples. Such external input signals can be input in synchronism with the rising edge of the external clock signal CLK. By inputting such external input signals, the synchronous semiconductor memory can execute control commands obtained by particular combinations of such external input signals.
A conventional synchronous semiconductor memory can also have a power-down mode. A power down mode may be entered by the clock enable signal CKE transitioning from an active level (high, for example) to an inactive level (low, for example). When the clock enable signal CKE transitions low, the signals .phi.4 and .phi.7 transition high, with a delay of about one cycle. The signal .phi.4, which mask controls the internal clock signal .phi.5, enables the internal clock signal .phi.5 to become inactive (high, for example). A high internal clock signal .phi.5 can essentially stop the active operation of internal circuits, placing the synchronous semiconductor memory in a power-down mode.
Within the third control circuit 818, the resulting .phi.2, .phi.4 and .phi.6 signals can result in the control signal .phi.7 being driven to an inactive level (high, for example). An inactive control signal .phi.7 can result in other initial circuits being placed in an inactive state.
In this way, a synchronous semiconductor memory that is executing control commands can be stopped by a transition in the clock enable signal CKE. In the event the synchronous semiconductor memory includes complementary metal-oxide-semiconductor (CMOS) circuits, such CMOS circuits can hold current data. Further, current consumption, due to the charging and discharging of various nodes, can be essentially eliminated. In addition, other initial circuits (that can receive other external input signals) are also disabled, and consume essentially no current.
While conventional synchronous semiconductor memories can provide a power down mode, it is still desirable to arrive at some way of further reducing current consumption. Further reductions in current consumption in a power-down mode are desirable as a synchronous semiconductor memory may be utilized in a portable device that is powered by one or more batteries. By reducing power consumption, battery lifetime can be increased.
It is difficult to reduce the current consumption of the conventional clock control circuit 800 because the internal clock signal .phi.5, which is the main timing signal for the internal circuits, typically drives a relatively large load. In addition, devices within the first initial circuit 802, such as transistors, must be relatively large, as the .phi.1 signal must be supplied to two circuit stages (i.e., the first and second one-shot signal generating circuits 808 and 810). Another reason power can be consumed arises from the first initial circuit 802. While internal circuits may be suspended in a power-down mode, the first initial circuit 802 may continue to compare the periodic external clock signal CLK to a reference voltage VREF, and amplify the result to generate the signal .phi.1. Such periodic comparing and amplifying can continue to consume current, and hence consume power.
It would be desirable to arrive at a clock control circuit for a synchronous semiconductor device that can reduce current consumption over conventional approaches. Such a clock control circuit could provide more advantageous power consumption characteristics and/or increase battery life for portable systems that include such synchronous semiconductor devices.